Systems Design Engineer

THE ROLE:

We are seeking a Senior Hardware Engineer to join the Data Center Systems Engineering team. In this role, you will lead the design, development, and integration of critical hardware technologies that power next-generation AI and accelerated computing platforms. You will contribute to the architecture and delivery of industry-leading Data Center GPU systems, working in a highly dynamic, fast-paced environment alongside cross-functional engineering teams. This position offers the opportunity to influence product strategy, drive technical execution, and solve complex system-level challenges from concept through production.

THE PERSON:

The ideal candidate is a highly motivated, self-directed engineering leader witha strong foundationin hardware design and extensive experience developing complex computing systems. Youpossessexceptional collaboration, communication, and organizational skills, enabling you to effectively drive alignment across multiple engineering disciplines.

You bring a minimum of five years of hardware design experience, coupled with deep technicalexpertisein computer architecture, signal integrity, power delivery, and system-level design. You thrive in environments with evolving requirements and are comfortable balancing technical rigor with execution agility while adhering toestablishedengineering processes and best practices.

Proficiencywith the Cadence design suite anddemonstratedexperience leading complex hardware development programs are essential.

KEY RESPONSIBILITIES:

• Lead the design and development of Data Center GPU platforms, accelerator cards, and supporting system hardware from concept through production.

• Collaborate with silicon architecture, firmware, software, mechanical, thermal, manufacturing, validation, and program management teams to define and deliver system solutions.

• Develop product requirements, technical specifications, schedules, and engineering execution plans.

• Drive schematic design,componentselection, and implementation of complex high-speed digital, power, and management circuits.

• Partner withcomponentsuppliers and technology vendors to evaluate solutions, review designs, and ensure successful implementation.

• Oversee PCB layout activities, ensuring compliance with signal integrity, power integrity, thermal, manufacturability, and reliability requirements.

• Work closely with Signal Integrity (SI) and Power Engineering teams to implementrobusthigh-speed interfaces and power delivery architectures.

• Drive Design for Manufacturing (DFM), Design for Test (DFT), reliability analysis, andcomponentderating reviews.

• Plan and lead board bring-up, system integration, validation, and qualification activities.

• Lead root-cause analysis and debug efforts for complex hardware issues using advanced laboratory instrumentation and diagnostic methodologies.

• Present technical reviews and project status updates to engineering leadership and key stakeholders.

PREFERRED QUALIFICATIONS:

• Direct experience designing Data Center GPU platforms and a strong understanding of AI server and rack-scale architectures.

• Working knowledge of platform management and firmware technologies, including Redfish, telemetry, platform monitoring, and system management architectures.

• Experience debugging andvalidatinghigh-speed interfaces, including PCI Express, XGMI, LPDDR, and related protocols.

• Strong understanding of high-speed design methodologies, PHY architectures, transmitter equalization, receiver signal processing, and advanced channel characterization techniques.

• Experience measuring and analyzing high-speed link performance using industry-standard metrics, including Vertical Eye (V-Eye) and Horizontal Eye (H-Eye) analysis.

• Experience developing FPGA-based subsystems, including RTL design, verification, and validation.

• Familiarity with Agile PLM or similar systems for BOM,componentlifecycle, and materials management.

• Experience leading complex cross-functional hardware development efforts from architecture through production release.