New 
Applications Engineering, Sr Staff Engineer-Physical Design, Synthesis
 Synopsys | |
$136000-$204000
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 United States, Texas, Austin | |
 May 22, 2026 | |
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We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.You AreYou have spent years deep in the RTL to GDSII flow and you know where things break. Not theoretically, actually. You have debugged synthesis runs that should have closed but didn't, traced timing violations back to their root cause, and explained to a frustrated design team why their netlist won't converge without making them feel like they missed something obvious. You think like a designer but communicate like someone who has sat across from customers who need answers today, not next week.You are comfortable moving between Fusion Compiler, PrimeTime, and Formality without losing sight of what the customer is actually trying to accomplish. When someone sends you a cryptic error log at 4pm, you do not panic. You ask three clarifying questions, reproduce it locally if you can, and either solve it or escalate it to R&D with enough context that they can act on it immediately.You do not wait for perfect documentation. You read between the lines, test assumptions, and build solutions that work in the real constraints customers face, not the ideal ones described in the user guide. At Synopsys, you will work directly with the teams building the chips that power everything, and what you solve today will unblock someone's tapeout tomorrow.What You'll Be DoingDiagnose and resolve complex technical issues across the full RTL to GDSII flow on live customer designs, working with tools like Fusion Compiler, IC Compiler II, PrimeTime, and StarRCDeploy new product releases and advanced node methodologies at customer sites, training design teams on implementation strategies, timing closure techniques, and power optimization workflowsWork directly with R&D to reproduce customer-reported bugs, validate fixes, and influence the technical roadmap based on real deployment feedbackReview customer design methodologies and provide recommendations on synthesis strategies, floorplanning approaches, CTS optimization, and signoff closurePartner with Sales and customer technical leads to scope proof-of-concept engagements, evaluate design challenges, and build technical solutions that support new account acquisitionScript automation workflows in Perl, Tcl, or Python to improve customer productivity, streamline debug processes, or replicate complex design scenariosPresent technical solutions, design trade-offs, and product capabilities to customer engineering teams and managementThe Impact You Will HaveYou will directly unblock critical tapeout schedules by resolving technical issues that would otherwise delay customer milestones by weeksYour deployment and training work will accelerate customer adoption of advanced node flows, improving their PPA results and reducing their overall design cycle timeThe feedback you surface from customer engagements will shape product priorities and influence the roadmap for tools used across the semiconductor industryYou will enable Sales to close strategic accounts by providing the technical credibility and proof points that turn evaluations into partnershipsYour collaboration with R&D will improve product quality and reliability, reducing the volume of escalations and support cases across the customer baseYou will build long-term customer relationships grounded in trust and technical depth, turning one-time engagements into multi-year partnershipsThe methodologies and scripts you develop will be reused across customer accounts, multiplying your impact beyond individual engagementsWhat You'll NeedTypically requires a bachelor's degree and a minimum of 8 years of related experience or an advanced degree and a minimum of 6 years of related experience.Hands-on experience across the full RTL to GDSII flow, including synthesis, place and route, static timing analysis, power analysis, and physical verificationStrong working knowledge of Synopsys tools such as Fusion Compiler, Design Compiler, IC Compiler II, PrimeTime, StarRC, Formality, or ICC2Deep understanding of advanced node design challenges including FinFET effects, multi-patterning, electromigration, and sub-10nm timing closure techniquesProficiency in scripting with Perl, Tcl, or Python to automate workflows, parse logs, or build custom analysis flowsExcellent verbal and written communication skills with the ability to explain timing paths, design trade-offs, and tool behavior to both engineers and managementExperience in ASIC implementation domains beyond physical design, such as RTL coding, verification, or formal checking, is a plusWillingness to travel occasionally to customer sites for deployment, training, or technical escalationsWho You AreYou can walk into a room where a design team is stuck on a timing closure issue and within 30 minutes identify whether it's a methodology problem, a tool issue, or a design constraint that needs revisitingYou do not get flustered when a customer pushes back on your recommendation. You listen, ask clarifying questions, and either adjust your approach or explain the trade-off in terms they can act onYou are organized enough to juggle multiple customer escalations at once without dropping threads or losing track of who needs what by whenYou care about the details. You do not close a case until you understand why the issue happened, not just that it's resolvedYou are comfortable saying "I don't know, but I will find out" and then actually following through with the right answer, not a guessYou can explain a complex STA violation to a junior engineer in a way that teaches them something, and then turn around and brief a VP on the same issue in two sentences without losing the nuanceThe Team You'll Be Part OfYou will be part of a highly skilled and dedicated team of engineers focused on providing exceptional technical support and solutions to our customers. Our team collaborates closely with R&D, Sales, and Customer Success to drive product adoption and satisfaction. We value continuous learning, open communication, and a customer-centric approach in everything we do.Rewards and BenefitsWe offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. Apply Now | |