Quality Assurance Associate

Role Proficiency:

Execute any sized customer projects independently with minimum supervision. Guide team members technically in any field of VLSI Frontend Backend or Analog design

Outcomes:

1. As an Individual contributor take ownership for any one or more task/module of RTL Design/Module Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff. etc.; leading the team to achieve results.
2. Complete assigned tasks successfully and on-time within the defined domain(s)
3. Anticipate diagnose and resolve problems; coordinating as necessary with cross-functional teams
4. On time quality delivery approved by the project manager and client
5. Automate the design tasks flows and write scripts to generate reports
6. Come up with novel ideas to reduce design cycle time and cost accepted by UST Manager and Client
7. Write paper(s) file patent(s) and device new design approaches

Measures of Outcomes:

1. Quality -verified using relevant metrics by UST Manager / Client Manager
2. Timely delivery - verified using relevant metrics by UST Manager / Client Manager
3. Reduction in cycle time and cost using innovative approaches
4. Number of papers published
5. Number of patents filed
6. Number of trainings presented to team

Outputs Expected:

Quality of the deliverables:

1. Bugs present in the design / circuit design. Zero bug is expected from the client
2. Clean delivery of the design/module in-terms of ease in integration at the top level
3. Meeting functional spec / design guidelines 100% without any deviation or limitation
4. Documentation of the tasks and work performed

Timely delivery:

1. Meeting project timelines as laid out by the client or program manager
2. Meeting intermediate tasks delivery facilitating other team members to progress
3. Calling out for help and support in-case of delay in tasks delivery on a case to case basis

Team Work:

1. Participation in team work and supporting team members at the time of need
2. Anticipate when team may need support and discuss with project manager to resolve issues
3. Able to hand hold junior team members to explain the project tasks and support delivery

Innovation & Creativity:

1. Automating tasks to save design cycle time on repetitive work processes
2. Participation in technical discussion
   training
   forum
   white paper or patent filing

Skill Examples:

1. Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice
2. EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (experience with one or more tools)
3. Technical Knowledge:a. Implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Understand and implement Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong Physical Design / Circuit Design / Analog Layout Knowledged. Strong Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design
4. Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below
5. Strong communication skills and ability to interact with team members and clients equally
6. Strong analytical reasoning and problem-solving skills with attention to details
7. Well versed and able to efficiently use the available EDA Ability to deliver the tasks on-time per quality guidelines and GANTT
8. Ability to understand the standard specs and functional documents
9. Required technical skills and prior design knowledge to execute the assigned tasks
10. Ability to learn new skills in-case required technical skills are not present at a level needed to execute the project

Knowledge Examples:

• Have led and executed project(s) in any of the design by executing - RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.
  
  
  
  1. Understanding of the design flow and methodologies used in designing
  2. Understanding of the assigned tasks and a good knowledge to execute the project tasks assigned by the client / manager as per known skills
  
  
  
  
  Additional Comments:
  
  

  JD:- Validation engineer job description: Essential duties and responsibilities: * Understand system requirements, generating system and RTL design document. * RTL Development and develop test bench to support the verification and validation of sub system and RTL modules. * Deliver test specifications document and test objectives. * Align the development and validation process with cross-functional teams. * Create internal and external specifications & user documents. * Learn constantly, dive into new areas with unfamiliar technologies, and embrace the ambiguity of problem-solving. * Apply critical thinking to the results/data of competitive analysis for product development. * Work with cross-functional teams, including ASIC, Firmware, and Validation, to ensure seamless product development. Qualifications: REQUIRED: * Experience with FPGA system design from IP Integration to implementation, Verilog RTL based IP design, Verilog/System Verilog based testbench development * Experience with AMD Vivado & Vitis SDK & VItis AI tools. * Experience with C/C++ in developing Embedded FW & scripting automation using Python * Experience with Petalinux build flow , familiarity with Uboot, linux driver changes and FPGA SoC debugging. * Proven ability to work as part of a global team in multiple geographies * B.Tech. in Electronics , Electrical , Computer Science Engineering * Requires 8-10 years of experience in FPGA/RTL & TestBench/ embedded systems architecture * Multi-disciplinary experience, including Firmware, HW, and ASIC/FPGA design

  
  

Fpga Design,Verilog RTL based IP design,System Verilog