Formal Design Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences - from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges -striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.

Together, we advance your career.

THE ROLE:

The Graphic Memory Controller(GMC) is an IP that delivers into all SOCs that are shipped by AMD's Radeon Technology Group. We deliver discrete graphics, Data Center GPUs and Game Console APUs using a flexible controller design as the base for all our IP. We are looking for a design verification engineer in the Dram Controller IP at AMD's Santa Clara, CA Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features. This is a highly visible position in a growing team. Leadership opportunity is available.

We are seeking a highly skilled Formal Verification Expert to join our talented team as a Staff Engineer and technical lead. This role is crucial to ensuring IP quality through rigorous formal verification processes.

THE PERSON:

The successful candidate will play a key role in developing verification strategies, leading formal verification team, and collaborating across departments to ensure the highest quality standards.

KEY RESPONSIBILITIES:

• Lead formal verification team to ensure IP quality and project execution.
• Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc..
• Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies.
• Mentor and guide junior engineers in formal verification techniques and best practices.
• Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations.
• Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities.

PREFERRED EXPERIENCE:

• Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems.
• Proficiency in formal verification tools such as VC-Formal or JasperGoal
• Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python).

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Santa Clara, CA

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.