Principal Analog Engineer
 Microsoft | |
 United States, California, Mountain View | |
 Aug 14, 2025 | |
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OverviewMicrosoft is a highly innovative company that collaborates across disciplines to producecutting edgetechnology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality. We are looking for aPrincipal Analog Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in thiscutting-edgetechnical environment. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.
ResponsibilitiesEstablish yourself as an integral member of AI SoC design team for the development of AI components with focus on best-in-class IP selection, QA and ensuring smooth integration in the SoCs. Identifying new value-adding, best-in-class IPs in the areas of PLL, DTS, Droop-Detector, HBM4,224 G Ethernet, GPIOs etc Facilitate selection of the most suitable IPs for targeted SoC landing-zones Architect robust process for IP release, update, QA, integration and pre/post silicon validationsReview of analog IP related designs (signal and power integrity) at different stages of development cycle Review of integration of IPs on 2.5D/3D SoCsInteractions with leading IP vendor on bug/ intergration issuesTrack release and updates of the IPs and ensure appropriate integration Review of the IP integrations, signal and power integrity, package and board designs with experts in Microsoft team as well as team experts and IP vendors. Ensure quality of incoming IPs and facilitate smooth integrations by working closely with Logic design and Physical design teams. Interface with architecture, physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design Provide technical leadership through mentorship and teamwork | |