Principal Advanced Packaging Technology Engineer

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THE ROLE:

The job role will be responsible for advanced 2.5D & 3D IC packaging technology evaluation, design enablement, product development, and manufacturing bring-up for FPGA and ASIC products from concept through to production.
THE PERSON:

The candidate must pose deep expertise in advanced 2.5D & 3D packaging technologies including manufacturing flows, vendor eco-system, yield, reliability, and industry trend. Proficiency in CAD flows and EDA tools to support robust 3DIC product and package design is essential. Strong communication and interpersonal skills are required, along with the ability to collaborate effectively with cross-functional teams including design, foundry, packaging/assembly, and validation. A degree in engineering or physical science is required, with over 20 years of relevant experience preferred.

KEY RESPONSIBILITIES:
Define 2.5D & 3D IC advanced packaging technology and drive system-technology co-optimization (STCO) of FPGA and ASIC products at advanced nodes

• Collaborate with design, CAD, and PDK teams to enable EDA design and verification flows for 2.5D/3D IC packaging
• Support exploration and development of 3DIC and packaging technology roadmap
• Drive 2.5D & 3DIC technology validation and reliability assessment prior to production
• Drive product yield analysis and design enhancement through collaboration with foundry and design teams to meet product need

PREFERRED EXPERIENCE:

• Proven expertise in 2.5D & 3D packaging technologies such as CoWoS, SoIC, InFO and WoW, including manufacturing, design rules and reliability requirements
• Hands-on design experience with major EDA tools for 3DIC product/package design, physical verification, signal/power integrity analysis, reliability and thermal validation
• In-depth understanding of 2.5D & 3D IC product roadmap, challenges and solutions including cost, power delivery, thermal management etc.
• Working experience in 2.5D & 3D IC testchip and product design and product yield improvement is desirable
• Experience in packaging substrate design and co-optimization with 3DIC architectures
• Familiarity with advanced silicon nodes (e.g. 3nm, 2nm) is preferred
• Strong analytical, problem solving, decision-making and communication skills
• Prior team leadership and management experience is a plus

ACADEMIC CREDENTIALS:

• Bachelor's degree in engineering or physical science is required; an advanced degree (MS or PhD) is preferred

LOCATION:

San Jose, CA

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.