New

Senior Staff Physical Design Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, Idaho, Boise
700 South Clearwater Lane (Show on map)
May 15, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Marvell Physical Design team is located in our Boise, ID office, and has a long history of successful design tapeouts in advanced process nodes. Our team is made up of both newer and more experienced engineers with a broad depth of physical design engineering experience. Being a part of our team will give you a chance to work on many different aspects of the chip design process, while working alongside some of the best engineers in the industry. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor and data center chips in a leading-edge CMOS process technology. What You Can Expect This role is based in the Marvell office in Boise, ID. You will work with both local and global team members on the physical design of complex chips as well as the methodology to enable an efficient and robust design process. Key responsibilities include: Work with design teams across various disciplines such as Digital/RTL/Analog to ensure design convergence and integration in a timely manner. Implement/support designs with multi-voltage designs through all aspects of implementation (place and route, static timing, physical verification) using industry standard EDA tools. Work with RTL design teams to drive assembly and design closure. Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes. Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation. What We're Looking For Bachelor's Degree in Electrical/Computer Engineering plus 3-5 years of related experience, OR a Master's Degree in Electrical/Computer Engineering with 2-3 years related experience. Expertise in full-chip & sub-hierarchy integration. Experience integrating and taping out large designs utilizing a digital design environment. Good understanding of RTL to GDS flows and methodology. Good scripting skills in TCL/Python. Knowledge of Verilog. Experience with Cadence Innovus is preferred. Expected Base Pay Range (USD) 125,900 - 186,260, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-VM1